Field
Circuit devices and the manufacture and structure of circuit devices.
Background
Increased performance in circuit devices on a substrate (e.g., integrated circuit (IC) transistors, resistors, capacitors, etc. on a semiconductor (e.g., silicon) substrate) is typically a major factor considered during design, manufacture, and operation of those devices. For example, during design and manufacture or forming of metal oxide semiconductor (MOS) transistor devices, such as those used in a complementary metal oxide semiconductor (CMOS), it is often favored to increase movement of electrons in N-type MOS device (n-MOS) channels and to increase movement of positive charged holes in P-type MOS device (p-MOS) channels. A key parameter in assessing device performance is the current delivered at a given design voltage. This parameter is commonly referred to as transistor drive current or saturation current (IDsat). Drive current is affected by factors that include the transistor's channel mobility and external resistance. Thus, device performance is affected by channel mobility (e.g., carrier mobility in the channel between the source and drains); and the external resistance (Rext) (e.g., the external resistance seen between a contact to the source and a contact to the drain).
The mobility of carriers (i.e. holes and electrons) in the transistor's channel region may be affected by the channel material composition, doping, and strain (e.g. tensile or compressive strain). Increased carrier mobility translates directly into increased drive current at a given design voltage and gate length. Carrier mobility can be increased by straining the channel region's lattice. For p-MOS devices, carrier mobility (i.e. hole mobility) is enhanced by generating a compressive strain in the transistor's channel region. For n-MOS devices, carrier mobility (i.e. electron mobility) is enhanced by generating a tensile strain in the transistor's channel region.
Rext may be affected by channel material composition, doping, and strain. Rext may also be affected by source/drain material composition and doping; source/drain contact composition and doping; and interfaces between source/drain contacts and the source and drain material. External resistance may be referred to as the sum of: (1) the resistances associated with the ohmic contacts (metal to semiconductor and semiconductor to metal), (2) the resistance within the source/drain region itself, (3) the resistance of the region between the channel region and the source/drain regions (i.e. the tip region), and (4) the interface resistance due to impurity (carbon, nitrogen, oxygen) contamination at the location of the initial substrate-epi-layer interface.
Some transistors use a “quantum well” (QW), such as between a source and drain. A quantum well is a concept that includes design of a channel “stack” to confine an energy region for carriers that participate in transport, for a MOSFET device. Here the confined energy region (e.g. a layer) is a region with a lower bandgap that is confined between a top layer and a bottom layer, each having a higher bandgap. For example, a quantum well may include a layer of germanium (Ge) or a layer of silicon germanium (SiGe) between two layers of silicon. Alternatively, the quantum well may include a layer of indium gallium arsenide (InGaAs) between a top layer of indium phosphide (InP), and a bottom layer of indium aluminum arsenide (InAlAs). In each case, the top layer may be described as a “buffer” and/or top “barrier” layer to provide confinement of carriers in “channel” layer and also minimize scattering effect of defects in gate stack on the carrier mobility in the channel (e.g., for a buried channel structure). Also, the bottom layer may be described as a bottom “buffer” layer such as to provide confinement of carriers in “channel” layer (like the top layer) and also improve the electrostatic integrity by insulating the channel from the bulk (e.g., for a SOI like scheme).
Below the bottom buffer layer may be a substrate. The substrate may be a bulk style substrate or a silicon-on-insulator (SOI) substrate. The substrate may include a graded buffer below the QW bottom buffer. Below the graded buffer may be another buffer layer or a substrate layer, such as a silicon handle wafer. Alternatively, below the bottom barrier may be an insulator layer, and then a substrate, such as to form a silicon-on-insulator (SOI) or heterostructure-on-insulator (HOI) structure. Generally, layers below the QW bottom buffer layer may be described as the substrate, or as part of the substrate.